10 nm process

In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nm process as the MOSFET technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nm.

Semiconductor
device
fabrication
MOSFET scaling
(process nodes)
Future

All production "10 nm" processes are based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology. Samsung first started their production of 10 nm-class chips in 2013 for their multi-level cell (MLC) flash memory chips, followed by their SoCs using their 10 nm process in 2016. TSMC began commercial production of 10 nm chips in 2016, and Intel later began production of 10 nm chips in 2018.

Since 2009, however, "node" has become a commercial name for marketing purposes[1] that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch.[2][3][4] For example, GlobalFoundries' 7 nm processes are similar to Intel's 10 nm process, thus the conventional notion of a process node has become blurred.[5] TSMC and Samsung's 10 nm processes are somewhere between Intel's 14 nm and 10 nm processes in transistor density. The transistor density (number of transistors per square millimetre) is more important than transistor size, since smaller transistors no longer necessarily mean improved performance, or an increase in the number of transistors.

Background

Egyptian-American engineer Mohamed Atalla and Korean-American engineer Dawon Kahng (the original inventors of the MOSFET in 1959)[6] in 1962 demonstrated a device that has a metallic layer with nanometric thickness sandwiched between two semiconducting layers, with the metal forming the base and the semiconductors forming the emitter and collector. They deposited metal layers (the base) on top of single crystal semiconductor substrates (the collector), with the emitter being a crystalline semiconductor piece with a top or a blunt corner pressed against the metallic layer (the point contact). With the low resistance and short transit times in the thin metallic nanolayer base, the devices were capable of high operation frequency compared to bipolar transistors. The device demonstrated by Atalla and Kahng deposited gold (Au) thin films with a thickness of 10 nm on n-type germanium (n-Ge) and the point contact was n-type silicon (n-Si).[7]

In 1987, Iranian-American engineer Bijan Davari led an IBM research team that demonstrated the first MOSFET with a 10 nm gate oxide thickness, using tungsten-gate technology.[8]

In 2002, an international team of researchers at UC Berkeley, including Shibly Ahmed (Bangladeshi), Scott Bell, Cyrus Tabery (Iranian), Jeffrey Bokor, David Kyser, Chenming Hu (Taiwan Semiconductor Manufacturing Company), and Tsu-Jae King Liu, demonstrated the first FinFET with 10 nm gate length.[9][10]

The ITRS's original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm.

In 2008, Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, said that Intel saw a 'clear way' towards the 10 nm node.[11][12]

In 2011, Samsung announced plans to introduce the 10 nm process the following year.[13] In 2012, Samsung announced eMMC flash memory chips that are produced using the 10 nm process.[14]

In actuality, "10 nm" as it is generally understood in 2018 is only in high-volume production at Samsung. GlobalFoundries has skipped 10 nm, Intel has not yet started high-volume 10 nm production, due to yield issues, and TSMC has considered 10 nm to be a short-lived node,[15] mainly dedicated to processors for Apple during 2017–2018, moving on to 7 nm in 2018.

There is also a distinction to be made between 10 nm as marketed by foundries and 10 nm as marketed by DRAM companies.

Technology production history

In April 2013, Samsung announced that it had begun mass production of multi-level cell (MLC) flash memory chips using a 10 nm-class process, which, according to Tom's Hardware, Samsung defined as "a process technology node somewhere between 10-nm and 20-nm".[16] On 17 October 2016, Samsung Electronics announced mass production of SoC chips at 10 nm.[17] The technology's main announced challenge has been triple patterning for its metal layer.[18][19]

TSMC began commercial production of 10 nm chips in early 2016, before moving onto mass production in early 2017.[20]

On 21 April 2017, Samsung started shipping their Galaxy S8 smartphone which uses the company's version of the 10 nm processor.[21] On 12 June 2017, Apple delivered second-generation iPad Pro tablets powered with TSMC-produced Apple A10X chips using the 10 nm FinFET process.[22]

On September 12, 2017, Apple announced the Apple A11, a 64-bit ARM-based system on a chip, manufactured by TSMC using a 10 nm FinFET process and containing 4.3 billion transistors on a die of 87.66 mm2.

In April 2018, Intel announced a delay in volume production of 10 nm mainstream CPUs until sometime in 2019.[23] In July the exact time was further pinned down to the holiday season.[24] In the meantime, however, they did release a low-power 10 nm mobile chip, albeit exclusive to Chinese markets and with much of the chip disabled.[25]

In June 2018 at VLSI 2018, Samsung announced their 11LPP and 8LPP processes. 11LPP is a hybrid based on Samsung 14 nm and 10 nm technology. 11LPP is based on their 10 nm BEOL, not their 20 nm BEOL like their 14LPP. 8LPP is based on their 10LPP process.[26][27]

Nvidia released their GeForce 30 series GPUs in September 2020. They are made on a custom version of Samsung's 8nm process, called Samsung 8N, with a transistor density of 44.56 million transistors per mm2.[28][29]

10 nm process nodes

Foundry
ITRS Logic Device
Ground Rules (2015)		 Samsung TSMC Intel
Process name 16/14 nm 11/10 nm 10 nm 11 nm 8 nm 10 nm 10 nm[lower-alpha 1]
Transistor density (MTr / mm²) Un­known Un­known 51.82[27] 54.38[27] 61.18[27] 52.51[31] 100.8[32][lower-alpha 2]
Transistor Gate Pitch (nm) 70 48 68 ? 64 66 54
Interconnect pitch (nm) 56 36 51 ? ? 44 36
Transistor Fin Pitch (nm) 42 36 42 ? 42 36 34
Transistor Fin Height (nm) 42 42 49 ? ? Un­known 53
Production year 2015 2017 2017[27] 2018 2018 2016[lower-alpha 3]
2017[lower-alpha 4]		 2018
  1. Measurements of the process used for Cannon Lake in 2018. It is unclear whether these will be the same for Intel's next 10nm process in 2019.[30]
  2. Intel uses this formula:[33]
  3. accepting tape-outs[20]
  4. high volume shipment[20]

Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch). Samsung reported their 10 nm process as having a 64 nm transistor gate pitch and 48 nm interconnect pitch. TSMC reported their 10 nm process as having a 64 nm transistor gate pitch and 42 nm interconnect pitch. Further investigation by Tech Insights revealed these values to be false and they have been updated accordingly. In addition, the transistor fin height of Samsung's 10 nm process was updated by MSSCORPS CO at SEMICON Taiwan 2017.[34][35][36][37][38] GlobalFoundries decided not to develop a 10nm node, because it believed it would be short lived. [39] Samsung's 8nm process is the company's last to exclusively use DUV lithography.[40]

DRAM "10nm class"
Main article: Dynamic random-access memory

For the DRAM industry, the term "10 nm-class" is often used and this dimension generally refers to the half-pitch of the active area. The "10 nm" foundry structures are generally much larger.

Generally 10nm class refers to DRAM with a 10-19nm feature size, and was first introduced c. 2016. As of 2020 there are three generations of 10nm class DRAM : 1xnm (19-17nm, Gen1); 1ynm (16-14nm, Gen2); and 1znm (13-11nm, Gen3).[41] 3rd Generation "1z" DRAM was first introduced c.2019 by Samsung, and was initially stated to be produced using ArF lithography without the use of EUV lithography;[42][43] subsequent production did utilise EUV lithography.[44]

References
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  2. Shukla, Priyank. "A Brief History of Process Node Evolution". design-reuse.com. Retrieved 2019-07-09.
  3. Hruska, Joel. "14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists…". ExtremeTech.
  4. "Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022". wccftech.com. 2016-09-10.
  5. "Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms". eejournal.com. 2018-03-12.
  6. "1960: Metal Oxide Semiconductor (MOS) Transistor Demonstrated". The Silicon Engine. Computer History Museum. Retrieved August 31, 2019.
  7. Pasa, André Avelino (2010). "Chapter 13: Metal Nanolayer-Base Transistor". Handbook of Nanophysics: Nanoelectronics and Nanophotonics. CRC Press. pp. 13–1, 13–4. ISBN 9781420075519.
  8. Davari, Bijan; Ting, Chung-Yu; Ahn, Kie Y.; Basavaiah, S.; Hu, Chao-Kun; Taur, Yuan; Wordeman, Matthew R.; Aboelfotoh, O.; Krusin-Elbaum, L.; Joshi, Rajiv V.; Polcari, Michael R. (1987). "Submicron Tungsten Gate MOSFET with 10 nm Gate Oxide". 1987 Symposium on VLSI Technology. Digest of Technical Papers: 61–62.
  9. Tsu‐Jae King, Liu (June 11, 2012). "FinFET: History, Fundamentals and Future". University of California, Berkeley. Symposium on VLSI Technology Short Course. Retrieved 9 July 2019.
  10. Ahmed, Shibly; Bell, Scott; Tabery, Cyrus; Bokor, Jeffrey; Kyser, David; Hu, Chenming; Liu, Tsu-Jae King; Yu, Bin; Chang, Leland (December 2002). "FinFET scaling to 10 nm gate length" (PDF). Digest. International Electron Devices Meeting: 251–254. CiteSeerX 10.1.1.136.3757. doi:10.1109/IEDM.2002.1175825. ISBN 0-7803-7462-2. Archived from the original (PDF) on 2020-05-27. Retrieved 2019-10-12.
  11. Damon Poeter (July 2008). "Intel's Gelsinger Sees Clear Path To 10nm Chips". Archived from the original on 2009-06-22. Retrieved 2009-06-20.
  12. "MIT: Optical lithography good to 12 nanometers". Archived from the original on 2009-06-22. Retrieved 2009-06-20.
  13. "World's Largest Fabrication Facility, Line-16". Samsung. September 26, 2011. Retrieved 21 June 2019.
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  17. Samsung Starts Industry's First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology, Oct 2016
  18. Samsung 10nm announcement
  19. triple patterning for 10nm metal
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  21. "Buy".
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  29. https://wccftech.com/nvidia-geforce-rtx-30-series-ampere-graphics-cards-deep-dive/amp/
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  33. Bohr, Mark (2017-03-28). "Let's Clear Up the Node Naming Mess". Intel Newsroom. Retrieved 2018-12-06.
  34. "Intel Details Cannonlake's Advanced 10nm FinFET Node, Claims Full Generation Lead Over Rivals". 2017-03-28. Archived from the original on 2017-03-30. Retrieved 2017-03-30.
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  40. https://www.anandtech.com/show/11946/samsungs-8lpp-process-technology-qualified-ready-for-production
  41. Mellor, Chris (13 April 2020), "Why DRAM is stuck in a 10nm trap", blocksandfiles.com
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  43. Samsung Develops Industry’s First 3rd-generation 10nm-Class DRAM for Premium Memory Applications (press release), Samsung, 25 Mar 2019
  44. Samsung Announces Industry’s First EUV DRAM with Shipment of First Million Modules (press release), Samsung, 25 Mar 2020
Preceded by
14 nm		 MOSFET manufacturing processes Succeeded by
7 nm
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