Video Coding Engine
Video Code Engine (VCE, was earlier referred to as Video Coding Engine,[1] Video Compression Engine[2] or Video Codec Engine[3] in official AMD documentation) is AMD's video encoding ASIC implementing the video codec H.264/MPEG-4 AVC. Since 2012 it is integrated into all of their GPUs and APUs except Oland.
Video Coding Engine was introduced with the Radeon HD 7000 Series on 22 December 2011.[4][5][6] VCE occupies a considerable amount of the die surface and is not to be confused with AMD's Unified Video Decoder (UVD).
As of Raven Ridge (released January 2018), VCE has been succeeded by VCN.
Overview
The handling of video data involves computation of data compression algorithms and possibly of video processing algorithms. As the template Compression methods shows, lossy video compression algorithms involve the steps: Motion estimation (ME), Discrete cosine transform (DCT), and entropy encoding (EC).
AMD Video Code Engine (VCE) is a full hardware implementation of the video codec H.264/MPEG-4 AVC. The ASIC is capable of delivering 1080p at 60 frames/sec. Because its entropy encoding block is also a separately accessible Video Codec Engine, it can be operated in two modes: full-fixed mode and hybrid mode.[7][8]
By employing AMD APP SDK, available for Linux and Microsoft Windows, developers can create hybrid encoders that pair custom motion estimation, inverse discrete cosine transform and motion compensation with the hardware entropy encoding to achieve faster than real-time encoding. In hybrid mode, only the entropy encoding block of the VCE unit is used, while the remaining computation is offloaded to the 3D engine (GCN) of the GPU, so the computing scales with the number of available compute units (CUs).
VCE 1.0
As of April 2014, there are two versions of VCE.[1] Version 1.0 supports H.264 YUV420 (I & P frames), H.264 SVC Temporal Encode VCE, and Display Encode Mode (DEM).
It can be found on:
- Piledriver-based
- Trinity APUs (Ax-5xxx, e.g. A10-5800K)
- Richland APUs (Ax-6xxx, e.g. A10-6800K)
- GPUs of the Southern Islands generation (GCN1: CAYMAN, ARUBA (Trinity/Richland), CAPE VERDE, PITCAIRN, TAHITI). These are
- Radeon HD 7700 series (except HD 7790 with VCE 2.0)
- Radeon HD 7800 series
- Radeon HD 7900 series
- Radeon HD 8570 to 8990 (except HD 8770 with VCE 2.0)
- Radeon R7 250E, 250X, 265 / R9 270, 270X, 280, 280X
- Radeon R7 360, 370, 455 / R9 370, 370X
- Mobile Radeon HD 77x0M to HD 7970M
- Mobile Radeon HD 8000-Series
- Mobile Radeon Rx M2xx Series (except R9 M280X with VCE 2.0 and R9 M295X with VCE 3.0)
- Mobile Radeon R5 M330 to R9 M390
- FirePro cards with 1st Generation GCN (GCN1) (Except W2100, which is Oland XT)
VCE 2.0
Compared to the first version, VCE 2.0 adds H.264 YUV444 (I-Frames), B-frames for H.264 YUV420, and improvements to the DEM (Display Encode Mode), which results in a better encoding quality.
It can be found on:
- Steamroller-based
- Kaveri APUs (Ax-7xxx, e.g. A10-7850K)
- Godavari APUs (Ax-7xxx, e.g. A10-7890K)
- Jaguar-based
- Kabini APUs (e.g. Athlon 5350, Sempron 2650)
- Temash APUs (e.g. A6-1450, A4-1200)
- Puma-based
- Beema and Mullins
- GPUs of the Sea Islands generation as well Bonaire or Hawaii GPUs (2nd Generation Graphics Core Next), such as
- Radeon HD 7790, 8770
- Radeon R7 260, 260X / R9 290, 290X, 295X2
- Radeon R7 360 / R9 390, 390X
- Mobile Radeon R9 M280X
- Mobile Radeon R9 M385, M385X
- Mobile Radeon R9 M470, M470X
- FirePro cards with 2nd Generation GCN (GCN2)
VCE 3.0
Video Code Engine 3.0 (VCE 3.0) technology features a new high-quality video scaling and High Efficiency Video Coding (HEVC/H.265).[9]
It, together with UVD 6.0, can be found on 3rd generation of Graphics Core Next (GCN3) with "Tonga", "Fiji", "Iceland", and "Carrizo" (VCE 3.1) based graphics controller hardware, which is now used AMD Radeon Rx 300 Series (Pirate Islands GPU family) and VCE 3.4 by actual AMD Radeon Rx 400 Series and AMD Radeon 500 Series (both Polaris GPU family).
- Tonga: Radeon R9 285, 380, 380X; Mobile Radeon R9 M390X, M395, M395X, M485X
- Tonga XT: FirePro W7100, S7100X, S7150, S7150 X2
- Fiji: Radeon R9 Fury, Fury X, Nano; Radeon Pro Duo (2016); FirePro S9300, W7170M
- Polaris: RX 460, 470, 480; RX 550, 560, 570, 580; Radeon Pro Duo (2017)
VCE 4.0
The Video Code Engine 4.0 encoder and UVD 7.0 decoder are included in the Vega-based GPUs.[10][11]
VCE 4.1
AMD's Vega20 GPU, present in the Instinct Mi50, Instinct Mi60 and Radeon VII cards, include VCE 4.1 and two UVD 7.2 instances.[12][13]
APUs
The following table shows features of AMD's APUs (see also: List of AMD accelerated processing units).
Codename | Server | Basic | Toronto | |||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Micro | Kyoto | |||||||||||||||||||
Desktop | Performance | Renoir | ||||||||||||||||||
Mainstream | Llano | Trinity | Richland | Kaveri | Kaveri Refresh (Godavari) | Carrizo | Bristol Ridge | Raven Ridge | Picasso | |||||||||||
Entry | ||||||||||||||||||||
Basic | Kabini | |||||||||||||||||||
Mobile | Performance | Renoir | Cezanne | |||||||||||||||||
Mainstream | Llano | Trinity | Richland | Kaveri | Carrizo | Bristol Ridge | Raven Ridge | Picasso | ||||||||||||
Entry | Dalí | |||||||||||||||||||
Basic | Desna, Ontario, Zacate | Kabini, Temash | Beema, Mullins | Carrizo-L | Stoney Ridge | |||||||||||||||
Embedded | Trinity | Bald Eagle | Merlin Falcon, Brown Falcon |
Great Horned Owl | Grey Hawk | Ontario, Zacate | Kabini | Steppe Eagle, Crowned Eagle, LX-Family |
Prairie Falcon | Banded Kestrel | ||||||||||
Platform | High, standard and low power | Low and ultra-low power | ||||||||||||||||||
Released | Aug 2011 | Oct 2012 | Jun 2013 | Jan 2014 | 2015 | Jun 2015 | Jun 2016 | Oct 2017 | Jan 2019 | Mar 2020 | Jan 2021 | Jan 2011 | May 2013 | Apr 2014 | May 2015 | Feb 2016 | Apr 2019 | |||
CPU microarchitecture | K10 | Piledriver | Steamroller | Excavator | "Excavator+"[14] | Zen | Zen+ | Zen 2 | Zen 3 | Bobcat | Jaguar | Puma | Puma+[15] | "Excavator+" | Zen | |||||
ISA | x86-64 | x86-64 | ||||||||||||||||||
Socket | Desktop | High-end | N/A | |||||||||||||||||
Mainstream | N/A | FM2+[lower-alpha 1] | AM4 | |||||||||||||||||
Entry | FM1 | FM2 | FM2+[lower-alpha 2] | AM1 | ||||||||||||||||
Basic | N/A | N/A | ||||||||||||||||||
Other | FS1 | FS1+, FP2 | FP3 | FP4 | FP5 | FP6 | FT1 | FT3 | FT3b | FP4 | FP5 | |||||||||
PCI Express version | 2.0 | 3.0 | 4.0 | 2.0 | 3.0 | |||||||||||||||
Fab. (nm) | GF 32SHP (HKMG SOI) |
GF 28SHP (HKMG bulk) |
GF 14LPP (FinFET bulk) |
GF 12LP (FinFET bulk) |
TSMC N7 (FinFET bulk) |
TSMC N40 (bulk) |
TSMC N28 (HKMG bulk) |
GF 28SHP (HKMG bulk) |
GF 14LPP (FinFET bulk) | |||||||||||
Die area (mm2) | 228 | 246 | 245 | 245 | 250 | 210[16] | 156 | ? | 75 (+ 28 FCH) | 107 | ? | 125 | 149 | |||||||
Min TDP (W) | 35 | 17 | 12 | 10 | 4.5 | 4 | 3.95 | 10 | 6 | |||||||||||
Max APU TDP (W) | 100 | 95 | 65 | 18 | 25 | |||||||||||||||
Max stock APU base clock (GHz) | 3 | 3.8 | 4.1 | 4.1 | 3.7 | 3.8 | 3.6 | 3.7 | 3.8 | ? | 1.75 | 2.2 | 2 | 2.2 | 3.2 | 3.3 | ||||
Max APUs per node[lower-alpha 3] | 1 | 1 | ||||||||||||||||||
Max CPU[lower-alpha 4] cores per APU | 4 | 8 | 2 | 4 | 2 | |||||||||||||||
Max threads per CPU core | 1 | 2 | 1 | 2 | ||||||||||||||||
Integer structure | 3+3 | 2+2 | 4+2 | 4+2+1 | ? | 1+1+1+1 | 2+2 | 4+2 | ||||||||||||
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF | ||||||||||||||||||||
IOMMU[lower-alpha 5] | N/A | |||||||||||||||||||
BMI1, AES-NI, CLMUL, and F16C | N/A | |||||||||||||||||||
MOVBE | N/A | |||||||||||||||||||
AVIC, BMI2 and RDRAND | N/A | |||||||||||||||||||
ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERO | N/A | N/A | ||||||||||||||||||
WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMIT | N/A | N/A | ||||||||||||||||||
FPUs per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | ||||||||||||||
Pipes per FPU | 2 | 2 | ||||||||||||||||||
FPU pipe width | 128-bit | 256-bit | 80-bit | 128-bit | ||||||||||||||||
CPU instruction set SIMD level | SSE4a[lower-alpha 6] | AVX | AVX2 | SSSE3 | AVX | AVX2 | ||||||||||||||
3DNow! | 3DNow!+ | N/A | N/A | |||||||||||||||||
PREFETCH/PREFETCHW | ||||||||||||||||||||
FMA4, LWP, TBM, and XOP | N/A | N/A | N/A | N/A | ||||||||||||||||
FMA3 | ||||||||||||||||||||
L1 data cache per core (KiB) | 64 | 16 | 32 | 32 | ||||||||||||||||
L1 data cache associativity (ways) | 2 | 4 | 8 | 8 | ||||||||||||||||
L1 instruction caches per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | ||||||||||||||
Max APU total L1 instruction cache (KiB) | 256 | 128 | 192 | 256 | 512 | 64 | 128 | 96 | 128 | |||||||||||
L1 instruction cache associativity (ways) | 2 | 3 | 4 | 8 | 2 | 3 | 4 | |||||||||||||
L2 caches per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | ||||||||||||||
Max APU total L2 cache (MiB) | 4 | 2 | 4 | 1 | 2 | 1 | ||||||||||||||
L2 cache associativity (ways) | 16 | 8 | 16 | 8 | ||||||||||||||||
APU total L3 cache (MiB) | N/A | 4 | 8 | N/A | 4 | |||||||||||||||
APU L3 cache associativity (ways) | 16 | 16 | ||||||||||||||||||
L3 cache scheme | Victim | N/A | Victim | Victim | ||||||||||||||||
Max stock DRAM support | DDR3-1866 | DDR3-2133 | DDR3-2133, DDR4-2400 | DDR4-2400 | DDR4-2933 | DDR4-3200, LPDDR4-4266 | LPDDR4-4266 | DDR3L-1333 | DDR3L-1600 | DDR3L-1866 | DDR3-1866, DDR4-2400 | DDR4-2400 | ||||||||
Max DRAM channels per APU | 2 | 1 | 2 | |||||||||||||||||
Max stock DRAM bandwidth (GB/s) per APU | 29.866 | 34.132 | 38.400 | 46.932 | 68.256 | ? | 10.666 | 12.800 | 14.933 | 19.200 | 38.400 | |||||||||
GPU microarchitecture | TeraScale 2 (VLIW5) | TeraScale 3 (VLIW4) | GCN 2nd gen | GCN 3rd gen | GCN 5th gen[17] | TeraScale 2 (VLIW5) | GCN 2nd gen | GCN 3rd gen[17] | GCN 5th gen | |||||||||||
GPU instruction set | TeraScale instruction set | GCN instruction set | TeraScale instruction set | GCN instruction set | ||||||||||||||||
Max stock GPU base clock (MHz) | 600 | 800 | 844 | 866 | 1108 | 1250 | 1400 | 2100 | ? | 538 | 600 | ? | 847 | 900 | 1200 | |||||
Max stock GPU base GFLOPS[lower-alpha 7] | 480 | 614.4 | 648.1 | 886.7 | 1134.5 | 1760 | 1971.2 | 2150.4 | ? | 86 | ? | ? | ? | 345.6 | 460.8 | |||||
3D engine[lower-alpha 8] | Up to 400:20:8 | Up to 384:24:6 | Up to 512:32:8 | Up to 704:44:16[18] | Up to 512:32:8 | ? | 80:8:4 | 128:8:4 | Up to 192:?:? | Up to 192:?:? | ||||||||||
IOMMUv1 | IOMMUv2 | IOMMUv1 | ? | IOMMUv2 | ||||||||||||||||
Video decoder | UVD 3.0 | UVD 4.2 | UVD 6.0 | VCN 1.0[19] | VCN 2.0[20] | UVD 3.0 | UVD 4.0 | UVD 4.2 | UVD 6.0 | UVD 6.3 | VCN 1.0 | |||||||||
Video encoder | N/A | VCE 1.0 | VCE 2.0 | VCE 3.1 | N/A | VCE 2.0 | VCE 3.1 | |||||||||||||
AMD Fluid Motion | ||||||||||||||||||||
GPU power saving | PowerPlay | PowerTune | PowerPlay | PowerTune[21] | ||||||||||||||||
TrueAudio | N/A | [22] | N/A | |||||||||||||||||
FreeSync | 1 2 |
1 2 | ||||||||||||||||||
HDCP[lower-alpha 9] | ? | 1.4 | 1.4 2.2 | ? | 1.4 | 1.4 2.2 | ||||||||||||||
PlayReady[lower-alpha 9] | N/A | 3.0 not yet | N/A | 3.0 not yet | ||||||||||||||||
Supported displays[lower-alpha 10] | 2–3 | 2–4 | 3 | 3 (desktop) 4 (mobile, embedded) | 4 | 2 | 3 | 4 | ||||||||||||
/drm/radeon [lower-alpha 11][24][25] | N/A | N/A | ||||||||||||||||||
/drm/amdgpu [lower-alpha 11][26] | N/A | [27] | N/A | [27] |
- For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
- For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
- A PC would be one node.
- An APU combines a CPU and a GPU. Both have cores.
- Requires firmware support.
- No SSE4. No SSSE3.
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
- Unified shaders : texture mapping units : render output units
- To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
- To feed more than two displays, the additional panels must have native DisplayPort support.[23] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
- DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.
GPUs
The following table shows features of AMD's GPUs (see also: List of AMD graphics processing units).
Name of GPU series | Wonder | Mach | 3D Rage | Rage Pro | Rage | R100 | R200 | R300 | R400 | R500 | R600 | RV670 | R700 | Evergreen | Northern Islands |
Southern Islands |
Sea Islands |
Volcanic Islands |
Arctic Islands/Polaris |
Vega | Navi | Big Navi | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Released | 1986 | 1991 | 1996 | 1997 | 1998 | Apr 2000 | Aug 2001 | Sep 2002 | May 2004 | Oct 2005 | May 2007 | Nov 2007 | Jun 2008 | Sep 2009 | Oct 2010 | Jan 2012 | Sep 2013 | Jun 2015 | Jun 2016 | Jun 2017 | Jul 2019 | Nov 2020 | |||
Marketing Name | Wonder | Mach | 3D Rage | Rage Pro | Rage | Radeon 7000 | Radeon 8000 | Radeon 9000 | Radeon X700/X800 | Radeon X1000 | Radeon HD 2000 | Radeon HD 3000 | Radeon HD 4000 | Radeon HD 5000 | Radeon HD 6000 | Radeon HD 7000 | Radeon Rx 200 | Radeon Rx 300 | Radeon RX 400/500 | Radeon RX Vega/Radeon VII(7nm) | Radeon RX 5000 | Radeon RX 6000 | |||
AMD support | |||||||||||||||||||||||||
Kind | 2D | 3D | |||||||||||||||||||||||
Instruction set | Not publicly known | TeraScale instruction set | GCN instruction set | RDNA instruction set | |||||||||||||||||||||
Microarchitecture | TeraScale 1 | TeraScale 2 (VLIW5) | TeraScale 3 (VLIW4) | GCN 1st gen | GCN 2nd gen | GCN 3rd gen | GCN 4th gen | GCN 5th gen | RDNA | RDNA 2 | |||||||||||||||
Type | Fixed pipeline[lower-alpha 1] | Programmable pixel & vertex pipelines | Unified shader model | ||||||||||||||||||||||
Direct3D | N/A | 5.0 | 6.0 | 7.0 | 8.1 | 9.0 11 (9_2) |
9.0b 11 (9_2) |
9.0c 11 (9_3) |
10.0 11 (10_0) |
10.1 11 (10_1) |
11 (11_0) | 11 (11_1) 12 (11_1) |
11 (12_0) 12 (12_0) |
11 (12_1) 12 (12_1) |
11 (12_2) 12 (12_2) | ||||||||||
Shader model | N/A | 1.4 | 2.0+ | 2.0b | 3.0 | 4.0 | 4.1 | 5.0 | 5.1 | 5.1 6.3 |
6.4 | 6.5 | |||||||||||||
OpenGL | N/A | 1.1 | 1.2 | 1.3 | 2.0[lower-alpha 2] | 3.3 | 4.5 (on Linux + Mesa 3D: 4.5 with FP64 HW support, 4.3 without)[28][29][30][lower-alpha 3] | 4.6 (on Linux: 4.6 (Mesa 20.0)) | |||||||||||||||||
Vulkan | N/A | 1.0 (Win 7+ or Mesa 17+) |
1.2 (Adrenalin 20.1, Linux Mesa 20.0) | ||||||||||||||||||||||
OpenCL | N/A | Close to Metal | 1.1 | 1.2 | 2.0 (Adrenalin driver on Win7+) (on Linux: 1.2 with Mesa 3D, 2.1 with AMD drivers or AMD ROCm) |
? | 2.1 [31] | ||||||||||||||||||
HSA | N/A | ? | |||||||||||||||||||||||
Video decoding ASIC | N/A | Avivo/UVD | UVD+ | UVD 2 | UVD 2.2 | UVD 3 | UVD 4 | UVD 4.2 | UVD 5.0 or 6.0 | UVD 6.3 | UVD 7[10][lower-alpha 4] | VCN 2.0[10][lower-alpha 4] | VCN 3.0[32] | ||||||||||||
Video encoding ASIC | N/A | VCE 1.0 | VCE 2.0 | VCE 3.0 or 3.1 | VCE 3.4 | VCE 4.0[10][lower-alpha 4] | |||||||||||||||||||
Fluid Motion | |||||||||||||||||||||||||
Power saving | ? | PowerPlay | PowerTune | PowerTune & ZeroCore Power | ? | ||||||||||||||||||||
TrueAudio | N/A | Via dedicated DSP | Via shaders | ? | |||||||||||||||||||||
FreeSync | N/A | 1 2 | |||||||||||||||||||||||
HDCP[lower-alpha 5] | ? | 1.4 | 1.4 2.2 |
1.4 2.2 2.3 |
? | ||||||||||||||||||||
PlayReady[lower-alpha 5] | N/A | 3.0 | 3.0 | ? | |||||||||||||||||||||
Supported displays[lower-alpha 6] | 1–2 | 2 | 2–6 | ? | |||||||||||||||||||||
Max. resolution | ? | 2–6 × 2560×1600 |
2–6 × 4096×2160 @ 60 Hz |
2–6 × 5120×2880 @ 60 Hz |
3 × 7680×4320 @ 60 Hz[33] |
? | |||||||||||||||||||
/drm/radeon [lower-alpha 7] |
N/A | ||||||||||||||||||||||||
/drm/amdgpu [lower-alpha 7] |
N/A | Experimental[34] |
- The Radeon 100 Series has programmable pixel shaders, but do not fully comply with DirectX 8 or Pixel Shader 1.0. See article on R100's pixel shaders.
- These series do not fully comply with OpenGL 2+ as the hardware does not support all types of non-power of two (NPOT) textures.
- OpenGL 4+ compliance requires supporting FP64 shaders and these are emulated on some TeraScale chips using 32-bit hardware.
- The UVD and VCE were replaced by the Video Core Next (VCN) ASIC in the Raven Ridge APU implementation of Vega.
- To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
- More displays may be supported with native DisplayPort connections, or splitting the maximum resolution between multiple monitors with active converters.
- DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.
Operating system support
The VCE SIP core needs to be supported by the device driver. The device driver provides one or multiple interfaces, e. g. OpenMAX IL. One of these interfaces is then used by end-user software, like GStreamer or HandBrake (HandBrake rejected VCE support in December 2016,[35] but added it in December 2018[36]), to access the VCE hardware and make use of it.
AMD's proprietary device driver AMD Catalyst is available for multiple operating systems and support for VCE has been added to it. Additionally, a free device driver is available. This driver also supports the VCE hardware.
Linux
- Initial VCE support has been added on 4 February 2014 by Christian König of AMD to the free radeon driver.[37]
- Gallium3D state tracker for OpenMAX was added 24 October 2013 to Mesa 3D.[38]
- The free and open-source Radeon driver has been adapted to using OpenMAX with the GStreamer OpenMAX (gst-omx) support for exposing the VCE video encode engine.[39]
- AMD employee Leo Liu implemented h264 level support into the Mesa 3D state tracker.[40]
Windows
The software "MediaShow Espresso Video Transcoding" seems to utilize VCE and UVD to the fullest extent possible.[41]
XSplit Broadcaster supports VCE from version 1.3.[42]
Open Broadcaster Software (OBS Studio) supports VCE for recording and streaming. The original Open Broadcaster Software (OBS) requires a fork build in order to enable VCE.[43]
AMD Radeon Software supports VCE with built in game capture ("Radeon ReLive") and use AMD AMF/VCE on APU or Radeon Graphics card to reduce FPS drop when capturing game or video content.[44]
HandBrake added Video Coding Engine support in version 1.2.0 in December 2018.[36]
Successor
The VCE was succeeded by AMD Video Core Next in the Raven Ridge series of APUs released in October 2017. The VCN combines both encode (VCE) and decode (UVD).[45]
See also
- Intel Quick Sync Video – Intel's equivalent SIP core
- Nvidia NVENC – Nvidia's equivalent SIP core
References
- https://web.archive.org/web/20160604071338/http://developer.amd.com/community/blog/2014/02/19/introducing-video-coding-engine-vce/
- https://www.amd.com/en/media/43876/download
- https://subscriptions.amd.com/newsletters/channelnews/pdf_guides/51884i_update_to_the_qrg_october2014.pdf
- "White Paper AMD UnifiedVideoDecoder (UVD)" (PDF). 2012-06-15. Retrieved 2017-05-20.
- "AnandTech Portal | AMD Radeon HD 7970 Review: 28nm And Graphics Core Next, Together As One". Anandtech.com. Retrieved 2014-03-27.
- "AMD's Radeon HD 7970 graphics processor - The Tech Report - Page 5". The Tech Report. Retrieved 2014-03-27.
- "Video & Movies: The Video Codec Engine, UVD3, & Steady Video 2.0". AnandTech. December 22, 2011. Retrieved 2017-05-20.
- "Radeon HD 8900 Specs". AMD. Retrieved 2016-07-18.
- https://lists.freedesktop.org/archives/dri-devel/2015-June/084083.html [pull] amdgpu drm-next-4.2
- Killian, Zak (22 March 2017). "AMD publishes patches for Vega support on Linux". Tech Report. Retrieved 23 March 2017.
- Larabel, Michael (20 March 2017). "AMD Sends Out 100 Patches, Enabling Vega Support In AMDGPU DRM". Phoronix. Retrieved 25 August 2017.
- Deucher, Alex (15 May 2018). "[PATCH 50/57] drm/amdgpu/vg20:Enable the 2nd instance IRQ for uvd 7.2". Retrieved 2019-01-13.
- Deucher, Alex (15 May 2018). "[PATCH 42/57] drm/amd/include/vg20: adjust VCE_BASE to reuse vce 4.0 header files". Retrieved 2019-01-13.
- "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020.
- "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015.
- "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017.
- "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017.
- Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018.
- Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
- Liu, Leo (2020-09-04). "Add Renoir VCN decode support". Retrieved 2020-09-11.
It has same VCN2.x block as Navi1x
- Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016
- "A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014.
- "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 8 December 2014.
- Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 16 January 2016.
- "Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016.
- Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016.
- Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org.
- "AMD Radeon Software Crimson Edition Beta". AMD. Retrieved 2018-04-20.
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