Half-carry flag

A half-carry flag (also known as an auxiliary flag or decimal adjust flag) is a condition flag bit in the status register of many CPU families, such as the Intel 8080, Zilog Z80, the x86,[1] and the Atmel AVR series, among others. It indicates when a carry or borrow has been generated out of the least significant four bits of the accumulator register following the execution of an arithmetic instruction. It is primarily used in decimal (BCD) arithmetic instructions.

Usage

Normally, a processor that utilizes binary arithmetic (which includes almost all modern CPUs) will add two 8-bit byte values according to the rules of simple binary addition. For example, adding 2516 and 4816 produces 6D16. However, for binary-coded decimal (BCD) values, where each 4-bit nibble represents a decimal digit, addition is more complicated. For example, adding the decimal value 25 and 48, which are encoded as the BCD values 2516 and 4816, the binary addition of the two values produces 6D16. Since the lower nibble of this value is a non-decimal digit (D), it must be adjusted by adding 0616 to produce the correct BCD result of 7316, which represents the decimal value 73.

  0010 0101   25
+ 0100 1000   48
-----------
  0110 1101   6D, intermediate result
+      0110   06, adjustment
-----------
  0111 0011   73, adjusted result

Likewise, adding the BCD values 3916 and 4816 produces 8116. This result does not have a non-decimal low nibble, but it does cause a carry out of the least significant digit (lower four bits) into the most significant digit (upper four bits). This is indicated by the CPU setting the half-carry flag. This value must also be corrected, by adding 0616 to 8116 to produce a corrected BCD result of 8716.

  0011 1001   39
+ 0100 1000   48
-----------
  1000 0001   81, intermediate result
+      0110   06, adjustment
-----------
  1000 0111   87, adjusted result

Finally, if an addition results in a non-decimal high digit, then 6016 must be added to the value to produce the correct BCD result. For example, adding 7216 and 7316 produces E516. Since the most significant digit of this sum is non-decimal (E), adding 6016 to it produces a corrected BCD result of 14516. (Note that the leading 1 digit is actually a carry bit.)

  0111 0010   72
+ 0111 0011   73
-----------
  1110 0101   E5, intermediate result
+ 0110        60, adjustment
-----------
1 0100 0101  145, adjusted result

Summarizing, if the result of a binary addition contains a non-decimal low digit or causes the half-carry flag to be set, the result must be corrected by adding 0616 to it; if the result contains a non-decimal high digit, the result must be further corrected by adding 6016 to produce the correct final BCD value.

See also

References
  1. "Intel Architecture Software Developer's Manual, Volume 2: Instruction Set Reference Manual" (PDF). Retrieved 2013-05-29.
This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.